In semiconductor devices, aluminum and aluminum alloys have been used as the traditional interconnect metallurgies. While aluminum-based metallurgies have been the material of choice for use as metal interconnects over the past years, concern now exists as to whether aluminum will meet the demands required as circuit density and speeds for semiconductor devices increase. Because of these growing concerns, other materials have been investigated as possible replacements for aluminum-based metallurgies.
One highly advantageous material now being considered as a potential replacement for aluminum metallurgies is copper, because of its lower susceptibility to electromigration failure as compared to aluminum, as well as its lower resistivity.
Despite these advantages, copper suffers from an important disadvantage. Copper readily diffuses into the surrounding dielectric material during subsequent processing steps. To inhibit the diffusion of copper, copper interconnects are often capped with a protective barrier layer. One method of capping involves the use of a conductive barrier layer of tantalum, titanium or tungsten, in pure or alloy form, along the sidewalls and bottom of the copper interconnection. To cap the upper surface of the copper interconnection, a dielectric material such as silicon nitride (Si3N4) is typically employed.
FIG. 1 illustrates a conventional BEOL interconnect structure utilizing copper metallization and the protective cap layers described above. The interconnect structure comprises a lower substrate 10 which may contain logic circuit elements such as transistors. A dielectric layer 12, commonly known as an inter-level dielectric (ILD), overlies the substrate 10. ILD layer 12 may be formed of silicon dioxide (SiO2). However, in advanced interconnect structures, ILD layer 12 is preferably a low-k polymeric thermoset material such as SiLK™ (an aromatic hydrocarbon thermosetting polymer available from The Dow Chemical Company). An adhesion promoter layer 11 may be disposed between the substrate 10 and ILD layer 12. A layer of silicon nitride 13 is optionally disposed on ILD layer 12. Silicon nitride layer 13 is commonly known as a hardmask layer or polish stop layer. At least one conductor 15 is embedded in ILD layer 12. Conductor 15 is preferably copper in advanced interconnect structures, but alternatively may be aluminum or other conductive material. When conductor 15 is copper, a diffusion barrier liner 14 is preferably disposed between ILD layer 12 and conductor 15. Diffusion barrier liner 14 is typically comprised of tantalum, titanium, tungsten or nitrides of these metals. The top surface of conductor 15 is made coplanar with the top surface of silicon nitride layer 13, usually by a chemical-mechanical polish (CMP) step. A cap layer 16, also typically of silicon nitride, is disposed on conductor 15 and silicon nitride layer 13. Cap layer 16 acts as a diffusion barrier to prevent diffusion of copper from conductor 15 into the surrounding dielectric material during subsequent processing steps.
A first interconnect level is defined by adhesion promoter layer 11, ILD layer 12, silicon nitride layer 13, diffusion barrier liner 14, conductor 15, and cap layer 16 in the interconnect structure shown in FIG. 1. A second interconnect level, shown above the first interconnect level in FIG. 1, includes adhesion promoter layer 18, ILD layer 19, silicon nitride layer 20, diffusion barrier liner 21, conductor 22, and cap layer 23. The first and second levels may be formed by conventional damascene processes. For example, formation of the second interconnect level begins with deposition of adhesion promoter layer 18. Next, the ILD material 19 is deposited onto adhesion promoter layer 18. If the ILD material is a low-k polymeric thermoset material such as SILK™, the ILD material is typically spin-applied, given a post apply hot bake to remove solvent, and cured at elevated temperature. Next, silicon nitride layer 20 is deposited on the ILD. Silicon nitride layer 20, ILD layer 19, adhesion promoter layer 18 and cap layer 16 are then patterned, using a conventional photolithography and etching process, to form at least one trench and via. The trenches and vias are typically lined with diffusion barrier liner 21. The trenches and vias are then filled with a metal such as copper to form conductor 22 in a conventional dual damascene process. Excess metal is removed by a CMP process. Finally, cap layer 23 is deposited on copper conductor 22 and silicon nitride layer 20.
Due to the need for low temperature processing after copper deposition, cap layers are typically deposited at temperatures below 450° C. Accordingly, cap layer deposition is typically performed using plasma-enhanced chemical vapor deposition (PE CVD) or high density plasma chemical vapor deposition (HDP CVD) wherein the deposition temperature generally ranges from about 200° C. to about 500° C.
PE CVD and HDP CVD films have been used for many other applications in semiconductor device manufacturing. However, in using a cap layer such as silicon nitride for copper interconnects, conventional PE CVD or HDP CVD silicon nitride films create reliability problems.
HDP CVD films such as silicon nitride provide superior electromigration protection, as compared to PE CVD films, because HDP CVD films more readily stop the movement of copper atoms along the interconnect surface in the cap layer. However, in a conventional HDP deposition process, a seam is formed in the HDP CVD cap layer, and a crack in the cap layer often develops at this seam due to stress within the structure. If the crack develops in a portion of the cap layer overlying a copper conductor, the copper conductor may be readily exposed to moisture and other sources of oxygen. If the crack develops in a portion of the cap layer overlying the ILD, the copper conductor may be exposed to moisture diffusing through the ILD. In the latter case, the seam is of relatively minor concern in interconnect structures utilizing silicon dioxide as the ILD material, because the rate of moisture diffusion through silicon dioxide is very low. However, in interconnect structures utilizing low-k polymeric thermoset dielectric materials such as SiLK™, this seam is of greater concern, because the rate of moisture diffusion through most spin-on and CVD low-k materials is relatively high.
Moreover, any crack in the cap layer may lead to copper diffusion into the ILD through the seam. As a result of this copper diffusion, a copper nodule may form under the cap layer through the seams. This copper nodule may lead to leakage between adjacent interconnect lines.
Another significant disadvantage occurs when HDP CVD films are integrated with low-k dielectric materials. The energetic reactions of the HDP CVD process can enable interaction with and within the low-k materials causing undesirable changes to occur.
Such changes in low-k dielectric materials can be significantly mitigated by the use of PE CVD films. Moreover, in typical PE CVD films, no seam is formed during the deposition process. For this reason, PE CVD cap layers have been used to cap copper interconnect structures in earlier ground-rule devices, such as the 0.22 μm technology node. However, in more advanced ground-rule devices, such as the 0.18 μm technology node, PE CVD films have been found to be inferior to cap layers formed by other deposition techniques such as HDP CVD.
In particular, PE CVD films generally exhibit poorer adhesion to the copper surface. Typical PE CVD silicon nitride films exhibit adhesion values in the range of about 5 to less than 10 joules/m2, whereas typical HDP CVD silicon nitride films exhibit adhesion values of about 20 joules/m2, as determined by a four-point bend adhesion testing technique. PE CVD films may delaminate and form blisters over patterned copper lines, particularly during subsequent dielectric depositions, metallization, and chemical-mechanical polishing. After being deposited onto copper metallurgy, additional insulating layers generally will be deposited over the cap layer. However, subsequent deposition of insulating layers onto the cap layer will produce stress which can cause the cap layer to peel from the copper surface. This delamination results in several catastrophic failure mechanisms, including lifting interlayer dielectrics, lifting copper conductors, copper diffusion from uncapped copper lines, and electromigration. Such results are generally seen in dual damascene processing where delamination of the silicon nitride hardmask layer generally occurs during copper chemical-mechanical polishing.
Thus, there is a need in the art for an interconnect structure cap layer exhibiting the superior electromigration protection and adhesion characteristics of HDP CVD films, and the superior coverage of PE CVD films.